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  irfz46nspbf IRFZ46NLPBF hexfet ? power mosfet  advanced process technology  surface mount (irfz46ns)  low-profile through-hole (irfz46nl)  175c operating temperature  fast switching  fully avalanche rated  lead-free parameter typ. max. units r jc junction-to-case CCC 1.4 r ja junction-to-ambient ( pcb mounted,steady-state)** CCC 40 thermal resistance c/w parameter max. units i d @ t c = 25c continuous drain current, v gs @ 10v  53  i d @ t c = 100c continuous drain current, v gs @ 10v  37 a i dm pulsed drain current  180 p d @t a = 25c power dissipation 3.8 w p d @t c = 25c power dissipation 107 w linear derating factor 0.71 w/c v gs gate-to-source voltage 20 v i ar avalanche current  28 a e ar repetitive avalanche energy  11 mj dv/dt peak diode recovery dv/dt  5.0 v/ns t j operating junction and -55 to + 175 t stg storage temperature range soldering temperature, for 10 seconds 300 (1.6mm from case ) c absolute maximum ratings advanced hexfet ? power mosfets from international rectifier utilize advanced processing techniques to achieveextremely low on-resistance per silicon area. this benefit, combined with the fast switching speed and ruggedized device design that hexfet power mosfets are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. the d 2 pak is a surface mount power package capable of accommodating die sizes up to hex-4. it provides the highestpower capability and the lowest possible on-resistance in any existing surface mount package. the d 2 pak is suitable for high current applications because of its low internalconnection resistance and can dissipate up to 2.0w in a typical surface mount application. the through-hole version (irfz46nl) is available for low- profile applications. description v dss = 55v r ds(on) = 0.0165 ? i d = 53a  2 d pak to-262 s d g 04/22/04 www.irf.com 1 pd - 95158 downloaded from: http:///
irfz46ns/lpbf 2 www.irf.com  starting t j = 25c, l = 389h r g = 25 ? , i as = 28a. (see figure 12)  repetitive rating; pulse width limited by max. junction temperature. ( see fig. 11 ) notes: ** when mounted on 1" square pcb (fr-4 or g-10 material ). for recommended footprint and soldering techniques refer to application note #an-994.  i sd 28a, di/dt 220a/s, v dd v (br)dss , t j 175c.  pulse width 400s; duty cycle 2%.  uses irfz46n data and test conditions.  this is a typical value at device destruction and representsoperation outside rated limits. this is a calculated value limited to tj = 175c.  calculated continuous current based on maximum allowable junction temperature. package limitation current is 39a. parameter min. typ. max. units conditions i s continuous source current mosfet symbol (body diode) CCC CCC showing the i sm pulsed source current integral reverse (body diode)  CCC CCC p-n junction diode. v sd diode forward voltage CCC CCC 1.3 v t j = 25c, i s = 28a, v gs = 0v  t rr reverse recovery time CCC 67 101 ns t j = 25c, i f = 28a q rr reverse recovery charge CCC 208 312 nc di/dt = 100a/s  t on forward turn-on time intrinsic turn-on time is negligible (turn-on is dominated by l s +l d ) source-drain ratings and characteristics a parameter min. typ. max. units conditions v (br)dss drain-to-source breakdown voltage 55 CCC CCC v v gs = 0v, i d = 250a ? v (br)dss / ? t j breakdown voltage temp. coefficient CCC 0.057 CCC v/c reference to 25c, i d =1ma  r ds(on) static drain-to-source on-resistance CCC CCC .0165 ? v gs =10v, i d = 28a  v gs(th) gate threshold voltage 2.0 CCC 4.0 v v ds = v gs , i d = 250a g fs forward transconductance 19 CCC CCC s v ds = 25v, i d = 28a  CCC CCC 25 a v ds = 55v, v gs = 0v CCC CCC 250 v ds = 44v, v gs = 0v, t j = 150c gate-to-source forward leakage CCC CCC 100 v gs = 20v gate-to-source reverse leakage CCC CCC -100 na v gs = -20v q g total gate charge CCC CCC 72 i d = 28a q gs gate-to-source charge CCC CCC 11 nc v ds = 44v q gd gate-to-drain ("miller") charge CCC CCC 26 v gs = 10v, see fig. 6 and 13  t d(on) turn-on delay time CCC 14 CCC v dd = 28v t r rise time CCC 76 CCC i d = 28a t d(off) turn-off delay time CCC 52 CCC r g = 12 ? t f fall time CCC 57 CCC r d = 0.98 ?, see fig. 10  between lead, CCC CCC and center of die contact c iss input capacitance CCC 1696 CCC v gs = 0v c oss output capacitance CCC 407 CCC pf v ds = 25v c rss reverse transfer capacitance CCC 110 CCC ? = 1.0mhz, see fig. 5  e as single pulse avalanche energy  CCC 583  152 i as = 28a, l = 389mh electrical characteristics @ t j = 25c (unless otherwise specified) i gss ns i dss drain-to-source leakage current nh 7.5 l s internal source inductance 53 180 s d g downloaded from: http:///
irfz46ns/lpbf www.irf.com 3 fig 1. typical output characteristics fig 3. typical transfer characteristics 1 10 100 1000 0.1 1 10 100 i , drain-to-source current (a) d v , drain-to-source volta g e ( v ) ds vgs to p 15v 10v 8.0v 7.0v 6.0v 5.5v 5.0v bo ttom 4.5v 20 s pulse w idth t = 25c c a 4.5v 1 10 100 1000 0.1 1 10 100 4.5v i , drain-to-source current (a) d v , drain-to-source volta g e ( v ) ds vgs top 15v 10v 8.0v 7.0v 6.0v 5.5v 5.0v bottom 4.5v 20 s pulse w idth t = 175c c a 0.0 0.5 1.0 1.5 2.0 2.5 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 j t , junction temperature (c) r , drain-to-source on resistance ds(on) (n orm alized) v = 10v gs a i = 46a d 1 10 100 1000 4567891 0 t = 25c j gs v , gate-to-source volta g e ( v ) d i , drain-to-source c urrent (a) t = 175c j a v = 25v 20s pulse w idth ds fig 4. normalized on-resistance vs. temperature fig 2. typical output characteristics t j = 25c t j = 175c downloaded from: http:///
irfz46ns/lpbf 4 www.irf.com fig 7. typical source-drain diode forward voltage fig 5. typical capacitance vs. drain-to-source voltage fig 8. maximum safe operating area fig 6. typical gate charge vs. gate-to-source voltage 0 4 8 12 16 20 0 1 02 03 04 05 06 0 q , total gate char g e ( nc ) g v , g ate-to-source voltage (v) gs a for test circuit s ee figure 13 v = 44v v = 28v i = 28 a d dsds 1 10 100 1000 0.4 0.8 1.2 1.6 2.0 2.4 t = 25c j v = 0v gs v , source-to-drain volta g e (v) i , reverse drain current (a) sd sd a t = 175c j 1 10 100 1000 1 10 100 v , drain-to-source volta g e ( v ) ds i , drain current (a) ope ration in this area limite d by r d ds(on) 10s 100s 1ms 10ms a t = 25c t = 175c sin g le p u ls e cj 0 400 800 1200 1600 2000 2400 2800 1 10 100 c, capacitance (pf) ds v , drain-to-source volta g e ( v ) a v = 0v , f = 1mhz c = c + c , c shorte d c = c c = c + c gs iss g s g d ds rss g d oss ds g d c iss c oss c rss downloaded from: http:///
irfz46ns/lpbf www.irf.com 5 fig 9. maximum drain current vs. case temperature fig 10a. switching time test circuit v ds 90%10% v gs t d(on) t r t d(off) t f fig 10b. switching time waveforms fig 11. maximum effective transient thermal impedance, junction-to-case v ds pulse width 1 s duty factor 0.1 % r d v gs r g d.u.t. 10v + - v dd 0.01 0.1 1 10 0.00001 0.0001 0.001 0.01 0.1 1  notes: 1. duty factor d = t / t 2. peak t = p x z + t 1 2 j dm thjc c  p t t dm 1 2 t , rectangular pulse duration (sec) thermal response (z ) 1 thjc 0.01 0.02 0.05 0.10 0.20 d = 0.50  single pulse (thermal response)          
  
         i d , drain current (a)   

downloaded from: http:///
irfz46ns/lpbf 6 www.irf.com fig 12a. unclamped inductive test circuit fig 12b. unclamped inductive waveforms fig 13a. basic gate charge waveform v ds l d.u.t. v dd i as t p 0.01 ? r g + - t p v ds i as v dd v (br)dss 10 v d.u.t. v ds i d i g 3ma v gs .3 f 50k ? .2 f 12v current regulator same type as d.u.t. current sampling resistors + - fig 13b. gate charge test circuit q g q gs q gd v g charge 10 v fig 12c. maximum avalanche energy vs. drain current 0 100 200 300 400 500 25 50 75 100 125 150 175 j e , single pulse avalanche energy (mj) as a startin g t , junction tem p erature ( c ) v = 25v i top 11a 20a bo tto m 28a dd d downloaded from: http:///
irfz46ns/lpbf www.irf.com 7 peak diode recovery dv/dt test circuit p.w. period di/dt diode recovery dv/dt ripple 5% body diode forward drop re-appliedvoltage reverserecovery current body diode forward current v gs =10v v dd i sd driver gate drive d.u.t. i sd waveform d.u.t. v ds waveform inductor curent d = p. w . period + - + + + - - - fig 14. for n-channel hexfets * v gs = 5v for logic level devices    r g v dd ? dv/dt controlled by r g ? driver same type as d.u.t. ? i sd controlled by duty factor "d" ? d.u.t. - device under test d.u.t circuit layout considerations ? low stray inductance ? ground plane ? low leakage inductance current transformer  * downloaded from: http:///
irfz46ns/lpbf 8 www.irf.com d 2 pak part marking information (lead-free) d 2 pak package outline note: "p " in as s embly line pos ition indicates "l ead- f ree" f530s t his is an irf 530s wit h lot code 8024 as s e mb le d on ww 02, 2000 in t h e as s e mb l y line "l" as s e mb l y lot code int e r nat ional rectifier logo part number dat e code ye ar 0 = 2000 wee k 02 line l or f530s a = assembly site code week 02 p = de s ignat e s l e ad -f r e e product (optional) rectifier int e rnat ional logo lot code assembly ye ar 0 = 2000 dat e code part number downloaded from: http:///
irfz46ns/lpbf www.irf.com 9 to-262 part marking information to-262 package outlinedimensions are shown in millimeters (inches) as s e mb l y lot code rect ifier int e r nat ional as s e mb le d on ww 19, 1997 note: "p" in as s embly line pos i ti on i ndi cates "l ead-f ree" in t h e as s e mb l y l ine "c" logo t h is is an irl 3103l lot code 1789 example: line c dat e code we e k 19 ye ar 7 = 1997 part number part number logo lot code as s e mb l y int e r nat ional rect ifier product (optional) p = de s ignat e s l e ad-f r e e a = as s e mb l y s it e code we e k 19 ye ar 7 = 1997 dat e code or downloaded from: http:///
irfz46ns/lpbf 10 www.irf.com data and specifications subject to change without notice. this product has been designed and qualified for the industrial market. qualification standards can be found on irs web site. ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252-7105 tac fax: (310) 252-7903 visit us at www.irf.com for sales contact information . 4/04 d 2 pak tape & reel information 3 4 4 trr feed direction 1.85 (.073) 1.65 (.065) 1.60 (.063) 1.50 (.059) 4.10 (.161) 3.90 (.153) trl feed direction 10.90 ( .429 ) 10.70 ( .421 ) 16.10 ( .63 4 ) 15.90 ( .62 6 ) 1.75 ( .0 69 ) 1.25 ( .0 49 ) 11.60 ( .457 ) 11.40 ( .449 ) 15.42 ( .609 ) 15.22 ( .601 ) 4.72 ( .136 ) 4.52 ( .178 ) 24.30 ( .957 ) 23.90 ( .941 ) 0.368 ( .0145 ) 0.342 ( .0135 ) 1.60 ( .063 ) 1.50 ( .059 ) 13.50 ( .532 ) 12.80 ( .504 ) 330.00 ( 14.173 ) max. 27.40 ( 1.079 ) 23.90 ( .941 ) 60.00 ( 2.362 ) min . 30.40 ( 1.197 ) m ax. 26.40 ( 1.039 ) 24.40 ( .961 ) notes : 1. comforms to eia-418. 2. controlling dimension: millimeter. 3. dimension measured @ hub. 4. includes flange distortion @ outer edge. downloaded from: http:///
note: for the most current drawings please refer to the ir website at: http://www.irf.com/package/ downloaded from: http:///


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